The Vodka is Good but the Meat is Rotten
Can you give me a verilog code file matching the following description :
module A has one output port named X and an input port named P.
It has an instance of module B named i_B. This module has an output port named Y and an input port named P. The Input port is connected to A's input port P and the output port of i_B named Y is connected to A's output port X.
Module B has an instance of module C named i_C. This module has an output port named Z and an input port named P. The input port P is connected to B's input port P and the output port of i_C is connected to B's output port Y.
Module C has an instance of module D named i_D. This module has an output port named W and an input port named P. The input port P is connected to C's input port P and the output port of i_C is connected to C's output port Z.
List the definitions of all modules in the same file
module A( input P, output X ); B i_B ( .P(P), .Y(X) ); endmodule module B( input P, output Y ); C i_C ( .P(P), .Z(Y) ); endmodule module C( input P, output Z ); D i_D ( .P(P), .W(Z) ); endmodule module D( input P, output W ); // Implementation of module D endmodule
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